1. Field of Invention
The present invention relates generally to a novel analog phase locked loop (PLL) clock recovery circuit having particular performance advantages when used in the acquisition of data signals transmitted over token-ring local area networks.
2. Brief Description of the Prior Art
Local-area networks (LAN) are communication systems for enabling data-processing devices, such as computer workstations, to communicate with each other through a communication (e.g. transmission) media. Data-processing devices in such networks are typically referred to as nodes or stations, and many such stations are likely to be relatively autonomous requiring communication with other stations only occasionally. Other stations may require more frequent communication, and the amount of communication required by a particular station can vary from time to time. In many local area network, stations can be easily added to, removed from, and moved from place to place within the network.
While there are numerous local area networks presently known, they can be classified into two general types. The first type of network is referred to as a "centralized network" which is characterized by the requirement of a centralized network controller which implements the network protocol. The second type of local area network is referred to as a "distributed network" which does not require a centralized network controller, and instead provides each station within the network with a communication controller having a medium access control (MAC) unit that locally implements the network protocol within each communication controller.
In a distributed local area network, packet switching is a technique commonly employed to dynamically allocate the communication medium of the network among multiple communicating stations. According to this technique, messages to be communicated between stations are partitioned (by the transmitting station's processor) into packets, having a fixed maximum size. The packets are then ascribed a station (i.e. source) identifier. The packets are then placed on the communication medium by the station's data communication controller. Such packets are then sensed and selectively processed by the data communication controller of the destination station in the network.
To more fully appreciate the problems associated with distributed local-area-networks, reference is made to FIGS. 1 through 3. In FIG. 1, a distributed local area-network is shown comprising a plurality of stations 1 (i.e. nodes A through F) which are operably associated with a communication medium 2, such a cable. While a number of network configurations are possible, a token-ring network configuration is schematically illustrated for purposes of illustration. As shown in FIG. 1A, each station generally comprises a host processor (e.g., CPU) 3, a program memory 4, a system memory 5, a communication controller 6, a system bus 7, and a transceiver 8. The processor, program memory and system memory are each associated with a system bus 7, and the system bus, in turn, is interfaced with data communication controller 6, as shown. The data communication controller is interfaced with the communication medium by way of the transceiver. Typically, the transceiver is suitably adapted to the particular characteristics of the communication medium 2 being employed in the network.
In general, the data communication controller is usually integrated into a system architecture and software environment by providing a means for supporting two independent data queues in software: a transmit queue and a receive queue. Each queue is associated with a process, namely, the transmit process and the receive process of the low-level software communications driver. The transmit and receive queues are managed by software in system memory and eventually meet the communication controller. The interface between the queues and the communications controller determines the behavior of the queues during the addition of receive elements and removal of transmit elements. Management of the transmit and receive queue elements at the level of the data communication controller can be achieved in a variety of ways. One way in particular is described in copending Application Serial No. 07/965,145 entitled "METHOD AND APPARATUS FOR BUFFERING DATA WITHIN STATIONS OF A COMMUNICATION NETWORK" filed Oct. 22, 1992, which is incorporated herein by reference.
In distributed communication networks utilizing multiple layer token-passing communication protocols, such as the IEEE 802.5 standard, data packets must be transmitted around the ring of stations shown in FIG. 1. In accordance with the IEEE 802.5 standard, data packets are always being transmitted and received within the token-ring network. During this process a token-packet is passed from one station to another station in order to transfer the right of a station to initiate the transmission of packets to a destination station in the token-ring network. In a physical and data-flow sense, each station acts as a single repeater in a ring of repeaters. To provide improved synchronization among the stations in the network, each station is required to first recover the phase and frequency of the clock from the data signal transmitted from the previous station, and then use the recovered clock to time the transmission of data to the next station in the token-ring network. Only one station (i.e. the "active" monitor) on the ring uses its own local crystal oscillator to time its own data transmission. Thus, it is this station whose clock is used to time all data packet transmissions within the token-ring network.
As shown in FIG. 2, transceiver 8 at each station in a token-ring network comprises a number of components, namely: a receiver amplifier 10 for amplifying analog data signal received from cable 2; a digitizer 11 for converting the amplified analog data signal into a digital data signal suitable for digital signal processing; a phase locked loop (PLL) clock recovery circuit 12 for recovering from the digital data signal, the clock signal having edge transitions corresponding to the edge transitions of the incoming digital data signal; a flip-flop circuit 13 for separating retimed binary data D.sub.2 from raw binary data stream D.sub.1 ; and a transmitter 14 for transmitting data on cable 2. As a result of time required to perform the data processing operations in the data communication controller at each station, each station introduces an inherent station delay between the receiver 10 and transmitter 14. For the purposes of analysis, this station delay can be modeled as a first-in-first-out buffer (FIFO) 15 as shown in FIG. 2.
As shown in FIG. 2A, conventional PLL clock recovery circuit 12 comprises a number of subcomponents, namely: a phase detector 17 for detecting the phase deviation (i.e. error) between each (i) incoming data edge of the (raw) digital data signal D.sub.1 and (ii) incoming clock edge in the recovered clock signal clock, and producing a control signal which is proportional to the detected phase error; a charge pump 18 for producing charge proportional to the phase error detected by the phase detector; a loop filter 19 for integrating the charge pump output and compensate for the dynamics of the PLL, and producing a control voltage; and a voltage controlled oscillator 20 coupled to the phase detector 17, for producing a phase locked recovered clock signal in response to the voltage produced by the loop filter. In general, the function of the loop filter is to permit fast locking of the recovered clock signal while avoiding frequency instability problems during steady state operation.
When such prior art PLL clock recovery circuits are used in the station transceivers of a token-ring local area network, a serious problem arises due to the variable data patterns (i.e. density) typically transmitted over the token-ring network. The problem, known as "phase slope accumulation" can be more readily appreciated with reference to the token-ring network of FIG. 1 and the transfer function diagram of the PLL clock recovery circuit, shown in FIG. 2. By definition, accumulated phase slope (APS) is the phenomena where the first derivative of the data-dependent, phase step response in a chain of PLL clock recovery circuits, reaches a certain theoretical limit, namely: ##EQU1## where .phi..sub.s is the phase step magnitude due to cable group delay characteristics, K is the open loop gain of each PLL, and .tau. is the station delay of each PLL clock recovery circuit. With reference to FIG. 3A, the open loop gain K in the PLL circuit can be approximated by the expression: ##EQU2## where I.sub.p is the charge pump current, k is the VCO gain, R is the loop filter resistor, and d is the data density measured as the number of clock cycles between adjacent data edges.
Accumulated phase slope in a token-ring network results in a corresponding phase offset between incoming data and clock edges, and severely limits the performance of each PLL clock recovery circuit in the network. A high degree of phase offset between incoming data and clock edges can either shift the sampling clock of the PLL data recovery circuit (12, 13) to a less than optimal sampling point, or cause the PLL clock recovery circuit 12 to loose its lock onto the recovered clock signal. The amount of phase offset caused by accumulated phase slope can be approximated by the expression: ##EQU3##
As can be seen from expression (1), phase slope accumulation (APS) can be limited by a judicious choice of open loop gain K. However, a lower open loop gain will increase the time it takes for the PLL clock recovery circuit to track a change in phase error between the incoming data and clock edges. For a single PLL clock recovery circuit, a trade-off between open loop gain and the rise time of the phase step response can usually be made with satisfactory results. However, in token-ring networks, each PLL clock recovery circuit must track raw digital data signals having data cycle widths which can vary from 2 to 1. As the open loop gain of a conventional charge-pump PLL clock recovery circuit is proportional to the data density d of the incoming data pattern, the gain of each PLL clock recovery circuit in the token-ring network will also vary from 2 to 1. However, in the case of a token-ring network, the trade-offs which can be made for a single PLL clock recovery circuit no longer hold. Therefore, when incoming data patterns characterized by high data cycle widths are received at a station transceiver, the performance of prior art PLL clock recovery circuit suffers due to an inability of prior art PLL clock recovery circuits to track the accumulated phase slope present in the raw data signal. Also, when data patterns characterized by low data cycle widths are received, prior art PLL clock recovery circuits generates excessive phase slope in the recovered clock signal.
Thus, there is a great need in the data communication art for an improved PLL clock recovery circuit that can be integrated within local area network transceiver in order to overcome the shortcomings and drawbacks of prior art techniques.